(PR) JEDEC Updates DDR5 MRDIMM Standards with New Interface Logic, Expands Roadmap

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced milestones from its JC-40 and JC-45 Committees for Logic and DRAM Modules: the publication of a new DDR5 multiplexed rank data buffer (MDB) standard; progress toward a multiplexed rank registering clock driver (MRCD) standard; and continued work on the DDR5 multiplexed rank DIMM (MRDIMM) Gen 2 roadmap to enable higher-bandwidth DDR5 MRDIMM designs.

• Published: JESD82-552 (DDR5MDB02) Multiplexed Rank Data Buffer
• Expected soon: JESD82-542 (DDR5MRCD02) Multiplexed Rank Registering Clock Driver
• In progress: MRDIMM Gen 2 module standard nearing completion
• In development: Gen 2 DDR5 MRDIMM raw card designs targeting 12,800 MT/s and MRDIMM Gen 3 module standard development, with the underlying memory interface logic nearing finalization